Signal dictionary
A practical Verilog glossary
These definitions are short orientation aids. Use the applicable language standard and tool documentation when exact semantics or support boundaries matter.
Language objects
Module
A design unit with ports, declarations, behavior, and possibly instances of other modules. Elaboration creates a hierarchy from module definitions.
Net
An object representing connectivity and driven values. Nets can resolve contributions from drivers according to their type.
Variable
An object assigned by procedural code. Exact declaration vocabulary differs across Verilog and SystemVerilog modes.
Continuous assignment
A driver that continuously reevaluates an expression as its inputs change, commonly used for combinational relationships on nets.
Procedural block
An initial or always process that executes statements in response to initialization, delays, or events.
Parameter
An elaboration-time value used to configure widths, capacities, behavior, or structure for an instance.
Generate
An elaboration mechanism that conditionally or repeatedly creates structure based on constant expressions.
Simulation and time
Elaboration
The phase that selects top-level units, resolves parameters and generate choices, binds instances, and constructs the runnable hierarchy.
Event scheduler
The simulator mechanism that orders evaluation and updates at a simulation time. Correct reasoning depends on scheduled regions, not file order.
Blocking assignment
A procedural assignment that completes before the next statement in that thread proceeds. It is often used to express ordered computation in combinational procedures.
Nonblocking assignment
A procedural assignment that evaluates its right-hand side and schedules the update. It is the usual representation for clocked state updates.
Delta cycle
An informal name for zero-time scheduling steps that allow dependent events to settle without advancing simulation time.
Timescale
The units and precision used to interpret delays. Mixed or implicit settings can create surprising rounding and timing behavior.
Four-state logic
A value system containing zero, one, unknown, and high impedance. Unknown propagation is a diagnostic signal, not merely visual noise.
Synthesis and implementation
RTL
Register-transfer level: a design abstraction describing clocked state and combinational transformations between state elements.
Synthesis
Transformation of supported HDL into a logic network, followed by optimization and mapping under constraints.
Inference
The synthesis tool's recognition of hardware such as registers, memories, muxes, arithmetic, or latches from source patterns.
Netlist
A structural representation of instances and connectivity, often produced after synthesis or implementation.
Timing constraint
A statement of clock, interface, exception, or environment assumptions used to analyze and optimize path timing.
Latch
Level-sensitive storage. In combinational RTL, an unintended latch is commonly inferred when an output is not assigned on every path.
ASIC and FPGA
An ASIC is an application-specific integrated circuit manufactured for its intended function. An FPGA is a field-programmable device configured after manufacture. They share HDL concepts but differ in implementation resources and flow.
IP core
A reusable hardware design block delivered as source, an intermediate representation, a netlist, or a model under defined integration and license terms.
Boundary scan
A standardized test-access approach using scan cells around device input and output boundaries to support board connection and device testing.
Deep submicron
A period term for semiconductor processes whose shrinking geometries made interconnect, signal integrity, power, and timing effects increasingly important to design tools.
Verification
Testbench
Code and supporting components that configure a design, provide stimulus, observe behavior, check results, and report outcomes.
Assertion
An executable statement of an invariant or temporal relationship that reports when observed behavior violates the property.
Scoreboard
A checker that compares observed transactions or results with a predicted model, often while accounting for latency and reordering.
Functional coverage
User-defined evidence that planned scenarios and combinations occurred. It complements rather than replaces checking.
Code coverage
Measurement of exercised implementation structures such as statements, branches, expressions, or state transitions.
Regression
A repeatable collection of checks run after changes to detect behavior that no longer satisfies expectations.
These terms interact. Elaboration creates the module hierarchy that simulation executes; an event scheduler updates nets and variables; a testbench observes that behavior; synthesis interprets a restricted description as a netlist; constraints guide later analysis; and coverage reports which planned evidence was actually exercised. Reading definitions as a connected flow is more useful than memorizing them in isolation.