EDA market map

The Verilog vendor landscape was a chain of specialized tools

Simulation was only one segment of a market that also sold synthesis, timing, formal verification, emulation, implementation, libraries, and integration infrastructure.

Abstract engineering nodes converging into several larger constellations
Tool categories overlap, combine, and change ownership while engineering roles remain recognizable.

Categories before company names

The most stable way to understand an EDA market is to begin with the problem being solved. Event-driven simulators compile and execute HDL models. Cycle-oriented and compiled approaches trade generality for throughput in suitable designs. Logic synthesis transforms RTL into a network that can be optimized and mapped. Timing tools evaluate path delays against clock and interface constraints. Formal tools explore state spaces or compare representations. Emulators and prototyping systems move selected workloads onto specialized hardware.

Verification products add stimulus generation, assertions, coverage, debug, model integration, and regression management. Implementation tools place, route, and analyze a design in the context of a target process or programmable device. Library and intellectual-property suppliers provide models and reusable blocks. Configuration, data-management, and workflow products connect these stages. A vendor list that flattens all of this into “Verilog tools” obscures the decisions a team actually has to make.

Evaluate the interfaces between tools

A feature matrix is only a beginning. Ask which language revisions and subsets are accepted, how libraries and compilation units are modeled, whether diagnostics can be automated, and which interchange formats are produced. Check support for assertions, coverage, foreign-language interfaces, waveform databases, timing annotation, encrypted models, and the operating systems used by the team. Confirm that licenses and batch execution behave predictably under peak regression load.

Then test the seams. A synthesized netlist needs compatible cell models and timing data. A verification environment needs reliable access to hierarchy and simulator callbacks. A waveform database needs viewers that can handle its scale. A formal engine needs assumptions and abstractions that match the design. Debug metadata must survive enough of the flow to connect a failing low-level signal to the source-level intent.

Ownership changes require another layer of due diligence. A familiar product name may move into a larger portfolio, combine with another line, or stop receiving the attention implied by old documentation. The technically honest question is not whether a historic brand once served a category, but who maintains the relevant capability now and under which support terms. Company names below are therefore period context rather than recommendations.

Procurement and technical evaluation should proceed together. A tool that performs well in a demonstration may still conflict with the team's license topology, remote execution model, operating systems, security controls, or support response requirements. Conversely, an attractive commercial agreement cannot make an incompatible language front end or unstable regression interface acceptable. Write acceptance criteria that both engineering and operations can test.

Data longevity matters because projects often outlive releases. Ask which source, constraint, assertion, coverage, waveform, and database formats are open enough to inspect or migrate. Preserve scripts and textual reports wherever possible. A result that can only be understood inside one discontinued viewer creates a future verification problem even if it is convenient today.

Run upgrades against a qualification suite before changing the default environment. Compare diagnostics, elaborated hierarchy, simulation outcomes, coverage models, synthesis reports, and timing constraints. Record intentional differences and keep the prior flow available long enough to investigate regressions. The cost of qualification is part of the tool's real lifecycle cost.

Support evaluation should use real failure scenarios. Ask how a vendor receives a reproducible case, protects confidential design material, communicates known defects, and identifies a fixed release. Internally, assign an owner for each major tool boundary so license trouble, model incompatibility, and regression failures do not fall between organizational teams.

Shortlist rule: Build a representative acceptance suite from your own code and automation. Marketing categories are broad; compatibility failures are specific.

A period directory by function

Simulation

Cadence, Chronologic, Fintronic, Frontline, InterHDL, Mentor Graphics, Model Technology, Silos, Simucad, Synopsys, and Wellspring appeared among simulator or closely related listings.

Verification

0-In, Chrysalis, Quickturn, Real Intent, Verisity, and Verplex represented formal checking, emulation, coverage, or other verification-focused approaches of the period.

Design flow

Avant!, Synplicity, Synopsys, Exemplar, Viewlogic, and related suppliers appeared across synthesis, implementation, libraries, and broader EDA infrastructure.

Utilities

Smaller companies and independent utilities handled source processing, connectivity, model generation, editors, and interfaces around the major engines.

Examples of consolidation

Several names in the period directory later became parts of larger portfolios. These primary records give dated examples without implying that every older product survived unchanged.